Please use this identifier to cite or link to this item:
http://idr.mnit.ac.in/jspui/handle/123456789/525
Title: | Frequency sweep and width Optimization of memos based Digital logic gates… |
Authors: | Mali, Rajveer Bhargava, Prof. Lava |
Issue Date: | 1-Jun-2019 |
Publisher: | MNIT Jaipur |
Gov't Doc #: | 2017PEV5210 |
URI: | http://hdl.handle.net/123456789/525 |
Appears in Collections: | Frequency sweep and width Optimization of memos based Digital logic gates… |
Files in This Item:
File | Description | Size | Format | |
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2017PEV5210- Rajveer Mali.pdf | 2017PEV5210- Rajveer Mali | 2.44 MB | Adobe PDF | View/Open |
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