Please use this identifier to cite or link to this item:
http://idr.mnit.ac.in/jspui/handle/123456789/539
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sharma, Shashank | - |
dc.date.accessioned | 2020-03-11T03:20:12Z | - |
dc.date.available | 2020-03-11T03:20:12Z | - |
dc.date.issued | 2019-08-01 | - |
dc.identifier.govdoc | 2016PEV5392 | - |
dc.identifier.uri | http://hdl.handle.net/123456789/539 | - |
dc.language.iso | en_US | en_US |
dc.publisher | MNIT Jaipur | en_US |
dc.title | Simulation and Performance Investigation of Double Gate Junctionless Transistor for Ultra-Low Power… | en_US |
dc.type | Thesis | en_US |
dc.contributor.guide | Sahu, Dr. Chitrakant | - |
Appears in Collections: | Simulation and Performance Investigation of Double Gate Junctionless Transistor for Ultra-Low Power… |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
2016PEV5392- Shashank Sharma.pdf | 2016PEV5392- Shashank Sharma | 734.75 kB | Adobe PDF | View/Open |
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