IDR MNIT
→
Ph.D Theses of MNIT Jaipur
→
Electronics & Communication Engineering
→
On Efficient And Accurate Surrogate Models Of Leakage In CMOS Gated Circuits...
→
Browsing On Efficient And Accurate Surrogate Models Of Leakage In CMOS Gated Circuits... by Author

Browsing On Efficient And Accurate Surrogate Models Of Leakage In CMOS Gated Circuits... by Author "Professor, Dr. Vineet Sahula"

Now showing items 1-1 of 1

On Efficient And Accurate Surrogate Models Of Leakage In CMOS Gated Circuits...

Garg, Lokesh (MNIT Jaipur, 2016-05-01)

Now showing items 1-1 of 1

Search DSpace

Advanced Search

Browse

All of DSpace
This Collection
- By Issue Date
- Authors
- Titles
- Subjects

My Account