Please use this identifier to cite or link to this item:
http://idr.mnit.ac.in/jspui/handle/123456789/167Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Garg, Lokesh | - |
| dc.date.accessioned | 2017-07-06T04:37:32Z | - |
| dc.date.available | 2017-07-06T04:37:32Z | - |
| dc.date.issued | 2016-05-01 | - |
| dc.identifier.govdoc | ID - 2010REC101 | - |
| dc.identifier.uri | http://hdl.handle.net/123456789/167 | - |
| dc.language.iso | en | en_US |
| dc.publisher | MNIT Jaipur | en_US |
| dc.title | On Efficient And Accurate Surrogate Models Of Leakage In CMOS Gated Circuits... | en_US |
| dc.type | Thesis | en_US |
| dc.contributor.guide | Professor, Dr. Vineet Sahula | - |
| Appears in Collections: | On Efficient And Accurate Surrogate Models Of Leakage In CMOS Gated Circuits... | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 2010REC101 - Lokesh Garg.pdf | 2010REC101 - Lokesh Garg | 3.75 MB | Adobe PDF | View/Open |
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