Please use this identifier to cite or link to this item: http://idr.mnit.ac.in/jspui/handle/123456789/509
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dc.contributor.authorKumar, Naveen-
dc.date.accessioned2020-03-11T01:26:17Z-
dc.date.available2020-03-11T01:26:17Z-
dc.date.issued2019-07-01-
dc.identifier.govdoc2017PEV5175-
dc.identifier.urihttp://hdl.handle.net/123456789/509-
dc.language.isoen_USen_US
dc.publisherMNIT Jaipuren_US
dc.titleSimulation-Based Study of High Performance Double Gated Fd-Soi Transistor for Ph Sensing Applications…en_US
dc.typeThesisen_US
dc.contributor.guidePeriasamy, Dr. C.-
Appears in Collections:Simulation-Based Study of High Performance Double Gated Fd-Soi Transistor for Ph Sensing Applications…

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