1. Institutional Digital Repository of MNIT Jaipur
  2. M. Tech. Dissertation of MNIT Jaipur
  3. Electronics & Communication Engineering
  4. Simulation and Performance Investigation of Double Gate Junctionless Transistor for Ultra-Low Power…
Please use this identifier to cite or link to this item: http://idr.mnit.ac.in/jspui/handle/123456789/539
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dc.contributor.authorSharma, Shashank-
dc.date.accessioned2020-03-11T03:20:12Z-
dc.date.available2020-03-11T03:20:12Z-
dc.date.issued2019-08-01-
dc.identifier.govdoc2016PEV5392-
dc.identifier.urihttp://hdl.handle.net/123456789/539-
dc.language.isoen_USen_US
dc.publisherMNIT Jaipuren_US
dc.titleSimulation and Performance Investigation of Double Gate Junctionless Transistor for Ultra-Low Power…en_US
dc.typeThesisen_US
dc.contributor.guideSahu, Dr. Chitrakant-
Appears in Collections:Simulation and Performance Investigation of Double Gate Junctionless Transistor for Ultra-Low Power…

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