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Please use this identifier to cite or link to this item: http://idr.mnit.ac.in/jspui/handle/123456789/945
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dc.contributor.authorSharma, Ashish-
dc.date.accessioned2021-01-28T10:40:42Z-
dc.date.available2021-01-28T10:40:42Z-
dc.date.issued2019-08-01-
dc.identifier.govdoc2013RCP9515-
dc.identifier.urihttp://hdl.handle.net/123456789/945-
dc.language.isoenen_US
dc.publisherMNIT,Jaipuren_US
dc.titleReliability-aware Analysis And Design Of Network-on-chip…en_US
dc.typeThesisen_US
dc.contributor.guideGaur, Prof. Manoj Singh-
dc.contributor.guideBhargava, Prof. Lava-
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