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  2. Ph.D Theses of MNIT Jaipur
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  4. Nbti Aware Support Vector Machine Based Surrogate Model For Analog Circuits...
Please use this identifier to cite or link to this item: http://idr.mnit.ac.in/jspui/handle/123456789/656
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dc.contributor.authorKhandelwal, Sapna-
dc.date.accessioned2020-12-22T05:11:55Z-
dc.date.available2020-12-22T05:11:55Z-
dc.date.issued2018-09-01-
dc.identifier.govdoc2012REC9045-
dc.identifier.urihttp://hdl.handle.net/123456789/656-
dc.language.isoenen_US
dc.publisherMNIT, Jaipuren_US
dc.titleNbti Aware Support Vector Machine Based Surrogate Model For Analog Circuits...en_US
dc.typeThesisen_US
dc.contributor.guideBoolchandani, Prof. Dharmendar-
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